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| (R) (R) ADS-933 16-Bit, 3MHz Sampling A/D Converters INNOVATION and EXCELLENCE PRELIMINARY PRODUCT DATA FEATURES * * * * * * * * * 16-bit resolution 3MHz sampling rate Functionally complete No missing codes over full military temperature range Edge-triggered 5V supplies, 1.85 Watts Small, 40-pin, ceramic TDIP 85dB SNR, -84dB THD Ideal for both time and frequency-domain applications PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 INPUT/OUTPUT CONNECTIONS FUNCTION +3.2V REF. OUT UNIPOLAR ANALOG INPUT ANALOG GROUND OFFSET ADJUST GAIN ADJUST DIGITAL GROUND FIFO/DIR FIFO READ FSTAT1 FSTAT2 START CONVERT BIT 16 (LSB) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 PIN 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 FUNCTION NO CONNECTION NO CONNECTION +5V ANALOG SUPPLY -5V SUPPLY ANALOG GROUND COMP. BITS OUTPUT ENABLE OVERFLOW EOC +5V DIGITAL SUPPLY DIGITAL GROUND BIT 1 (MSB) BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 GENERAL DESCRIPTION The low-cost ADS-933 is a 16-bit, 3MHz sampling A/D converter. This device accurately samples full-scale input signals up to Nyquist frequencies with no missing codes. The dynamic performance of the ADS-933 has been optimized to achieve a signal-to-noise ratio (SNR) of 85dB and a total harmonic distortion (THD) of -84dB. Packaged in a 40-pin TDIP, the functionally complete ADS-933 contains a fast-settling sample-hold amplifier, a subranging (two-pass) A/D converter, an internal reference, timing/control logic, and error-correction circuitry. Digital input and output levels are TTL. The ADS-933 only requires the rising edge of the start convert pulse to operate. Requiring only 5V supplies, the ADS-933 dissipates 1.85 Watts. The device is offered with a bipolar (2.75V) analog input range and a unipolar 0 to -5.5V input range. Models are available for use in either commercial (0 to +70C) or military (- 55 to +125C) operating temperature ranges. A proprietary, autocalibrating, error-correcting circuit enables the device to achieve specified performance over the full military temperature range. Typical applications include medical imaging, radar, sonar, communications and instrumentation. 10 FSTAT1 11 FSTAT2 GAIN ADJUST 6 GAIN ADJUST CKT. 8 FIFO/DIR 9 FIFO/READ 29 BIT 1 (MSB) 28 BIT 1 (MSB) +3.2V REF. OUT 1 POWER AND GROUNDING +5V ANALOG SUPPLY +5V DIGITAL SUPPLY -5V SUPPLY ANALOG GROUND DIGITAL GROUND NO CONNECTION 38 31 37 4, 36 7, 30 39, 40 UNIPOLAR 2 OFFSET ADJUST 5 OFFSET ADJUST CKT. 2-PASS ANALOG-TO-DIGITAL CONVERTER PRECISION +3.2V REFERENCE 27 BIT 2 26 BIT 3 25 BIT 4 CUSTOM GATE ARRAY 3-STATE OUTPUT REGISTER 24 BIT 5 23 BIT 6 22 BIT 7 21 BIT 8 20 BIT 9 19 BIT 10 18 BIT 11 17 BIT 12 16 BIT 13 15 BIT 14 14 BIT 15 OFFSET ADJUST 5 13 BIT 16 (LSB) 34 OUTPUT ENABLE 33 OVERFLOW ANALOG INPUT 3 S/H START CONVERT 12 EOC 32 COMP. BITS 35 TIMING AND CONTROL LOGIC Figure 1. ADS-933 Functional Block Diagram DATEL, Inc., Mansfield, MA 02048 (USA) * Tel: (508)339-3000, (800)233-2765 Fax: (508) 339-6356 * E-mail: sales@datel.com * Internet: www.datel.com (R) (R) ADS-933 ABSOLUTE MAXIMUM RATINGS PARAMETERS LIMITS UNITS Volts Volts Volts Volts C +5V Supply (Pins 31, 38) 0 to +6 -5V Supply (Pin 37) 0 to -6 Digital Inputs (Pins 8, 9, 12, 34, 35) -0.3 to +VDD +0.3 Analog Input (Pin 3) 5 Lead Temperature (10 seconds) +300 PHYSICAL/ENVIRONMENTAL PARAMETERS Operating Temp. Range, Case ADS-933MC ADS-933MM Thermal Impedance jc ca Storage Temperature Range Package Type Weight MIN. 0 -55 -- -- -65 TYP. -- -- 4 18 -- MAX. +70 +125 -- -- +150 UNITS C C C/Watt C/Watt C FUNCTIONAL SPECIFICATIONS +25C ANALOG INPUT Input Voltage Range Unipolar Bipolar Input Resistance Pin 3 Input ResistancePin 2 Input Capacitance DIGITAL INPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Start Convert Positive Pulse Width STATIC PERFORMANCE Resolution Integral Nonlinearity (fin = 10kHz) Differential Nonlinearity (fin = 10kHz) Full Scale Absolute Accuracy Bipolar Zero Error (Tech Note 2) (Unipolar offset spec same as Bipolar zero) Bipolar Offset Error (Tech Note 2) Gain Error (Tech Note 2) No Missing Codes (fin = 10kHz) DYNAMIC PERFORMANCE Peak Harmonics (-0.5dB) dc to 500kHz 500kHz to 1MHz Total Harmonic Distortion (-0.5dB) dc to 500kHz 500kHz to 1MHz Signal-to-Noise Ratio (w/o distortion, -0.5dB) dc to 500kHz 500kHz to 1MHz Signal-to-Noise Ratio (& distortion, -0.5dB) dc to 500kHz 500kHz to 1MHz Noise Two-Tone Intermodulation Distortion (fin = 200kHz, 240kHz, fs = 3MHz, -0.5dB) Input Bandwidth (-3dB) Small Signal (-20dB input) Large Signal (-0.5dB input) Feedthrough Rejection (fin = 1MHz) Slew Rate Aperture Delay Time Aperture Uncertainty S/H Acquisition Time ( to 0.001%FSR, 5.5V step) -- -- -- -- 81 81 78 78 -- -- -- -- -- -- -- -- -- -- -84 -84 -83 85 85 82 81 80 -87 9.8 10.2 90 120 +8 3 180 81 80 80 80 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -0.95 -- -- -- -- 16 16 1 0.5 0.15 0.1 0.1 0.15 -- -- -- +1.0 0.3 0.2 0.2 0.3 -- +2.0 -- -- -- 20 -- -- -- -- 50 -- +0.8 +20 -20 -- MIN. -- -- 655 418 -- TYP. 0 to -5.5 2.75 687 426 10 MAX. -- -- -- -- 15 40-pin, metal-sealed, ceramic TDIP 0.56 ounces (16 grams) (TA = +25C, VCC = 5V, +VDD = +5V, 3MHz sampling rate, and a minimum 3 minute warm-up unless otherwise specified.) 0 to +70C MIN. -- -- 655 418 -- TYP. 0 to -5.5 2.75 687 426 10 MAX. -- -- -- -- 15 -55 to +125C MIN. -- -- 655 418 -- TYP. 0 to -5.5 2.75 687 426 10 MAX. -- -- -- -- 15 UNITS Volts Volts pF +2.0 -- -- -- 20 -- -- -- -- 50 -- +0.8 +20 -20 -- +2.0 -- -- -- 20 -- -- -- -- 50 -- +0.8 +20 -20 -- Volts Volts A A ns -- -- -0.95 -- -- -- -- 16 16 1.5 0.5 0.3 0.2 0.2 0.3 -- -- -- +1.0 0.5 0.4 0.4 0.5 -- -- -- -0.95 -- -- -- -- 16 16 2 0.5 0.5 0.4 0.4 0.5 -- -- -- +1.5 0.8 0.6 0.6 0.8 -- Bits LSB LSB %FSR %FSR %FSR % Bits -86 -84 -84 -83 85 85 82 81 80 -87 9.8 10.2 90 120 +8 3 180 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -86 -84 -84 -83 85 85 82 81 80 -87 9.8 10.2 90 120 +8 3 180 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- dB dB dB dB dB dB dB dB Vrms dB MHz MHz dB V/s ns psrms ns 2 (R) (R) ADS-933 DYNAMIC PERFORMANCE (Cont.) ANALOG OUTPUT Overvoltage Recovery Time A/D Conversion Rate Internal Reference Voltage Drift External Current DIGITAL OUTPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Output Coding POWER REQUIREMENTS Power Supply Ranges } +5V Supply -5V Supply Power Supply Currents +5V Supply -5V Supply Power Dissipation Power Supply Rejection MIN. +25C TYP. MAX. MIN. 0 TO +70C TYP. MAX. -55 TO +125C MIN. TYP. MAX. UNITS -- 3 3.15 -- -- -- -- +3.2 30 5 333 -- -- -- -- -- 3 -- -- -- -- -- +3.2 30 5 333 -- -- -- -- -- 3 -- -- -- -- -- +3.2 30 5 333 -- -- -- -- ns MHz Volts ppm/C mA +2.4 -- -- -- -- -- +2.4 -- -- +2.4 -- -- -- +0.4 -- -- +0.4 -- -- +0.4 -- -4 -- -- -4 -- -- -4 -- +4 -- -- +4 -- -- +4 Offset Binary / Complementary Offset Binary / Two's Complement / Complementary Two's Complement Volts Volts mA mA +4.75 -4.75 -- -140 -- -- +5.0 -5.0 +220 -150 1.85 -- +5.25 -5.25 260 -- 2.0 0.07 +4.75 -4.75 -- -140 -- -- +5.0 -5.0 +220 -150 1.85 -- +5.25 -5.25 260 -- 2.0 0.07 +4.9 -4.9 -- -140 -- -- +5.0 -5.0 +220 -150 1.85 -- +5.25 -5.25 260 -- 2.0 0.07 Volts Volts mA mA Watts %FSR/%V Footnotes: All power supplies must be on before applying a start convert pulse. All supplies and the clock (START CONVERT) must be present during warm-up periods. The device must be continuously converting during this time. When COMP. BITS (pin 35) is low, logic loading "0" will be -350A. A 3MHz clock with a 50nsec positive pulse width is used for all production testing. See Timing Diagram for more details. Effective bits is equal to: (SNR + Distortion) - 1.76 + 20 log 6.02 Full Scale Amplitude Actual Input Amplitude This is the time required before the A/D output data is valid once the analog input is back within the specified range. The minimum supply voltages of +4.9V and -4.9V for VDD are required for -55C operation only. The minimum limits are +4.75V and -4.75V when operating at +125C. TECHNICAL NOTES 1. Obtaining fully specified performance from the ADS-933 requires careful attention to pc-card layout and power supply decoupling. The device's analog and digital ground systems are connected to each other internally. For optimal performance, tie all ground pins (2, 4, 7, 30 and 36) directly to a large analog ground plane beneath the package. Bypass all power supplies and the +3.2V reference output to ground with 4.7F tantalum capacitors in parallel with 0.1F ceramic capacitors. Locate the bypass capacitors as close to the unit as possible. 2. The ADS-933 achieves its specified accuracies without the need for external calibration. If required, the device's small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in Figure 2. When using this circuitry, or any similar offset and gain calibration hardware, make adjustments following warm-up. To avoid interaction, always adjust offset before gain. Tie pins 5 and 6 to ANALOG GROUND (pin 4) if not using offset and gain adjust circuits. 3. Pin 35 (COMP. BITS) is used to select the digital output coding format of the ADS-933. See Tables 2a and 2b. When this pin has a TTL logic "0" applied, it complements all of the ADS-933's digital outputs. When pin 35 has a logic "1" applied, the output coding is complementary offset binary. Applying a logic "0" to pin 35 changes the coding to offset binary. Using the MSB output (pin 29) instead of the MSB output (pin 28) changes the respective output codings to complementary two's complement and two's complement. Pin 35 is TTL compatible and can be directly driven with digital logic in applications requiring dynamic control over its function. There is an internal pull-up resistor on pin 35 allowing it to be either connected to +5V or left open when a logic "1" is required. 4. To enable the three-state outputs, connect OUTPUT ENABLE (pin 34) to a logic "0" (low). To disable, connect pin 34 to a logic "1" (high). 3 (R) (R) ADS-933 5. Applying a start convert pulse while a conversion is in progress (EOC = logic "1") will initiate a new and probably inaccurate conversion cycle. Data from both the interrupted and subsequent conversions will be invalid. 6. Do not enable/disable or complement the output bits or read from the FIFO during the conversion process (from the rising edge of EOC to the falling edge of EOC). 7. The OVERFLOW bit (pin 33) switches from 0 to 1 when the input voltage exceeds that which produces an output of all 1's or when the input equals or exceeds the voltage that produces all 0's. When COMP BITS is activated, the above conditions are reversed. FIFO immediately after the first conversion has been completed and remains there until the FIFO is read. If the output three-state register has been enabled (logic "0" applied to pin 34), data from the first conversion will appear at the output of the ADS-933. Attempting to write a 17th word to a full FIFO will result in that data, and any subsequent conversion data, being lost. Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both equal to "1"), it can be read by dropping the FIFO READ line (pin 9) to a logic "0" and then applying a series of 15 rising edges to the read line. Since the first data word is already present at the FIFO output, the first read command (the first rising edge applied to FIFO READ) will bring data from the second conversion to the output. Each subsequent read command/rising edge brings the next word to the output lines. After the 15th rising edge brings the 16th data word to the FIFO output, the subsequent falling edge on READ will update the status outputs (after a 20ns maximum delay) to FSTAT1 = 0, FSTAT2 = 1 indicating that the FIFO is empty. If a read command is issued after the FIFO empties, the last word (the 16th conversion) will remain present at the outputs. INTERNAL FIFO OPERATION The ADS-933 contains an internal, user-initiated, 18-bit, 16word FIFO memory. Each word in the FIFO contains the 16 data bits as well as the MSB and overflow bits. Pins 8 (FIFO/ DIR) and 9 (FIFO READ) control the FIFO's operation. The FIFO's status can be monitored by reading pins 10 (FSTAT1) and 11 (FSTAT2). When pin 8 (FIFO/DIR) has a logic "1" applied, the FIFO is inserted into the digital data path. When pin 8 has a logic "0" applied, the FIFO is transparent and the output data goes directly to the output three-state register (whose operation is controlled by pin 34 (ENABLE)). Read and write commands to the FIFO are ignored when the ADS-933 is operated in the "direct" mode. It takes a maximum of 20ns to switch the FIFO in or out of the ADS-933's digital data path. FIFO Reset Feature At any time, the FIFO can be reset to an empty state by putting the ADS-933 into its "direct" mode (logic "0" applied to pin 8, FIFO/DIR) and also applying a logic "0" to the FIFO READ line (pin 9). The empty status of the FIFO will be indicated by FSTAT1 going to a "0" and FSTAT2 going to a "1". The status outputs change 40ns after applying the control signals. FIFO Write and Read Modes Once the FIFO has been enabled (pin 8 high), digital data is automatically written to it, regardless of the status of FIFO READ (pin 9). Assuming the FIFO is initially empty, it will accept data (18-bit words) from the next 16 consecutive A/D conversions. As a precaution, pin 9 (which controls the FIFO's READ function) should not be low when data is first written to an empty FIFO. When the FIFO is initially empty, digital data from the first conversion (the "oldest" data) appears at the output of the FIFO Status, FSTAT1 and FSTAT2 Monitor the status of the data in the FIFO by reading the two status pins, FSTAT1 (pin 10) and FSTAT2 (pin 11). CONTENTS Empty (0 words) 0 0 0 4 (R) (R) ADS-933 CALIBRATION PROCEDURE Connect the converter per Figure 2. Any offset/gain calibration procedures should not be implemented until the device is fully warmed up. To avoid interaction, adjust offset before gain. The ranges of adjustment for the circuits in Figure 2 are guaranteed to compensate for the ADS-933's initial accuracy errors and may not be able to compensate for additional system errors. A/D converters are calibrated by positioning their digital outputs exactly on the transition point between two adjacent digital output codes. This is accomplished by connecting 20k +5V -5V +5V 20k -5V LED's to the digital outputs and performing adjustments until certain LED's "flicker" equally between on and off. Other approaches employ digital comparators or microcontrollers to detect when the outputs change from one code to the next. For the ADS-933, offset adjusting is normally accomplished when the analog input is 0 minus 1/2 LSB (-42V). See Table 2b for the proper bipolar output coding. Gain adjusting is accomplished when the analog input is at nominal full scale minus 11/2 LSB's (+2.749874V). Note: Connect pin 5 to ANALOG GROUND (pin 4) for operation without zero/offset adjustment. Connect pin 6 to pin 4 for operation without gain adjustment. 6 GAIN ADJUST +5V 4.7F 0.1F 31 +5V DIGITAL 5 OFFSET ADJUST DIGITAL 7, 30 GROUND + +5V 4.7F 38 0.1F +5V ANALOG + ANALOG 2, 4, 36 GROUND 37 -5V -5V 4.7F 0.1F ADS-933 34 8 10 11 1 0.1F 4.7F ENABLE FIFO/DIR FSTAT1 ANALOG INPUT FSTAT2 FIFO READ +3.2V REF. OUT START CONVERT 12 COMP. BITS 35 9 3 33 32 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 OVERFLOW EOC BIT 1 (MSB) BIT 1 (MSB) BIT2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 BIT 13 BIT 14 BIT 15 BIT 16 (LSB) Zero/Offset Adjust Procedure 1. Apply a train of pulses to the START CONVERT input (pin 12) so that the converter is continuously converting. 2. For zero/offset adjust, apply -42V to the ANALOG INPUT (pin 3). 3. Adjust the offset potentiometer until the code flickers between 1000 0000 0000 0000 and 0111 1111 1111 1111 with pin 35 tied high (complementary offset binary) or between 0111 1111 1111 1111 and 1000 0000 0000 0000 with pin 35 tied low (offset binary). 4. Two's complement coding requires using BIT 1 (MSB) (pin 29). With pin 35 tied low, adjust the trimpot until the output code flickers between all 0's and all 1's. +5V Gain Adjust Procedure 1. For gain adjust, apply +2.749874V to the ANALOG INPUT (pin 3). 2. Adjust the gain potentiometer until all output bits are 0's and the LSB flickers between a 1 and 0 with pin 35 tied high (complementary offset binary) or until all output bits are 1's and the LSB flickers between a 1 and 0 with pin 35 tied low (offset binary). 3. Two's complement coding requires using BIT 1 (MSB) (pin 29). With pin 35 tied low, adjust the gain trimpot until the output code flickers equally between 0111 1111 1111 1111 and 0111 1111 1111 1110. 4. To confirm proper operation of the device, vary the applied input voltage to obtain the output coding listed in Table 2b. Table 2b. Output Coding Figure 2. Connection Diagram Table 2a. Setting Output Coding Selection (Pin 35) OUTPUT FORMAT Complementary Offset Binary Offset Binary PIN 35 LOGIC LEVEL 1 0 1 0 Complementary Two's Complement (Using MSB, pin 29) Two's Complement (Using MSB, pin 29) OUTPUT CODING MSB 1111 1111 1111 LSB "1" to "0" 1110 0000 0000 1100 0000 0000 1000 0000 0000 0111 1111 1111 0100 0000 0000 0010 0000 0000 0000 0000 0000 LSB "0" to "1" 0000 0000 0000 LSB 1111 0000 0000 0000 1111 0000 0000 0001 0000 MSB LSB MSB LSB MSB LSB INPUT RANGE 2.75V +2.749916 +2.749874 +2.062500 +1.375000 0.000000 -0.000084 -1.375000 -2.062500 -2.749916 -2.749958 -2.750000 BIPOLAR SCALE +FS -1 LSB +FS -1 1/2 LSB +3/4 FS +1/2 FS 0 -1 LSB -1/2 FS -3/4 FS -FS +1 LSB -FS + 1/2 LSB -FS 0000 0000 0000 0000 LSB "0" to "1" 0001 1111 1111 1111 0011 1111 1111 1111 0111 1111 1111 1111 1000 000 000 0000 1011 1111 1111 1111 1101 1111 1111 1111 1111 1111 1111 1110 LSB "1" to "0" 1111 1111 1111 1111 COMP. OFF. BIN. 0111 1111 1111 1111 LSB "1" to "0" 0110 0000 0000 0000 0100 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1100 0000 0000 0000 1010 0000 0000 0000 1000 0000 0000 0001 LSB "0" to "1" 1000 0000 0000 0000 TWO'S COMP. 1000 0000 0000 0000 LSB "0" to "1" 1001 1111 1111 1111 1011 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0011 1111 1111 1111 0101 1111 1111 1111 0111 1111 1111 1110 LSB "1" to "0" 0111 1111 1111 1111 COMP. TWO'S COMP. OFFSET BINARY 5 (R) (R) ADS-933 THERMAL REQUIREMENTS All DATEL sampling A/D converters are fully characterized and specified over operating temperature (case) ranges of 0 to +70C and -55 to +125C. All room-temperature (TA = +25C) production testing is performed without the use of heat sinks or forced-air cooling. Thermal impedance figures for each device are listed in their respective specification tables. These devices do not normally require heat sinks, however, standard precautionary design and layout procedures should be used to ensure devices do not overheat. The ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. Electrically insulating, thermally-conductive "pads" may be installed underneath the package. Devices should be soldered to boards rather than "socketed", and of course, minimal air flow over the surface can greatly help reduce the package temperature. In more severe ambient conditions, the package/junction temperature of a given device can be reduced dramatically (typically 35%) by using one of DATEL's HS Series heat sinks. See Ordering Information for the assigned part number. See page 1-183 of the DATEL Data Acquisition Components Catalog for more information on the HS Series. Request DATEL Application Note AN-8, "Heat Sinks for DIP Data Converters," or contact DATEL directly, for additional information. N START CONVERT N+1 50ns typ. N+2 N+3 N+4 N+5 Acquisition Time 170ns typ. 20ns typ. INTERNAL S/H Hold 161ns typ. 53ns typ. EOC Conversion Time 178ns typ. 265ns typ. 20ns typ. OUTPUT DATA Data N-4 Valid Data N-3 Valid Data N-2 Valid Data N-1 Valid Data N Valid 68ns typ. Notes: 1. Scale is approximately 50ns per division. fs = 3MHz. Invalid Data 2. This device has three pipeline delays. Four start convert pulses (clock cycles) must be applied for valid data from the first conversion to appear at the output of the A/D. 3. The start convert positive pulse width must be between either 20 and 60nsec or 200 and 310nsec (when sampling at 3MHz) to ensure proper operation. For sampling rates lower than 3MHz, the start pulse can be wider than 310nsec, however a minimum pulse width low of 20nsec should be maintained. A 3MHz clock with a 50nsec positive pulse width is used for all production testing. Figure 3. ADS-933 Timing Diagram 6 R1 +5VA +5VF C15 0.1F 20 9 U2 8 7 DGND -15V C2 2.2F 5 AGND 4 DGND 0.1F 0.1F B1(MSB) 34 32 30 C16 0.1F 20 9 8 B2 B3 B4 B5 17 18 19 11 AB3 AB4 AB5 AB6 AB7 AB8 DGND AB16 AB15 AB14 AB13 L3 -5VA 74HC86 4 6 START U5 CONVERT 5 10 L4 +5VA 20mH C13 2.2F +5VA 1 OFFSET ADJUST 2 3 -5VA R4 20k 9 +5VF 13 12 3 -5VA DGND 14 U5 11 FST1 7 74HC86 DGND C8 0.1F DGND GAIN ADJUST +5VA 1 R5 20k 2 +5VF DGND 20mH AB12 AB11 AB10 74HC86 8 U5 FST2 AB9 C17 0.1F 20 9 8 7 6 5 4 3 2 11 1 U4 10 12 13 14 15 16 17 18 19 1 B9 B6 B10 B7 B11 B8 B12 B13 B14 DGND B16 (LSB) B15 B14 B13 B12 B11 B10 B9 FIF +5VD COMP 123 RD 123 J5 FIFO/DIR J4 READ 1 2 3 J2 1 2 3 J3 ENABLE COMPLIM B15 B16 (LSB) 4 START 2 1 3 16 14 18 17 15 13 12 11 10 8 6 9 7 5 DGND DGND ENABLE COMPLIM DGND 7 6 5 4 3 2 16 15 14 U3 13 B1 (MSB) 12 10 DGND B5 26 B6 24 B7 B8 20 22 COMP AB1 AB2 DGND AB3 +5VD AB5 AB6 AB7 AB1 AB8 AB2 +5VF AB4 B4 28 B2 B3 33 B1B MSB 31 OVRFLW 29 EOC 27 DGND 25 23 DGND DGND 21 DGND 19 P1 DGND AGND AGND DGND AGND SG6 AGND +3.2VREF 2 SG5 AGND 3 ANA IN 4 AGND 5 5 AGND 6 GAIN 7 2 1 FIF DGND RD READ 10 FSTAT1 11 FSTAT2 12 START AB16 LSB 14 B15 15 B14 16 B13 17 B12 18 B11 19 B10 20 B9 U6 B8 21 B7 22 B6 23 B5 24 B4 25 B3 26 B2 27 AB15 L1 +5VF 20mH AB12 L2 +5VD AB10 20mH AB9 C9 2.2F AB11 AB13 AB14 13 MSB 28 MSB 29 DGND 30 +5VD 31 9 EOC 32 FIFO/DIR 8 OF 33 3.3k R3 DGND ENABLE 34 COMP 35 6 OFFSET AGND 36 -5VA 37 -5VA +5VA 38 11 1 +5VA SG9 +5VF AGND NC 39 2 19 B1B MSB NC 1 40 3 18 OVRFLW UUT 17 16 6 15 C18 0.1F C19 0.1F C20 0.1F C14 2.2F C12 2.2F 14 +5VD C21 2.2F -5VA +5VA +5VD -5VA +5VA 13 -5VA SG8 C3 0.1F C4 2.2F 12 10 DGND SG7 +15V C1 2.2F R2 (R) AGND 2 7 AMPLIFIER OPTION AR1 6 3 4 74HCT573 ANALOG INPUT AGND (R) B2 2 AGND +5VF +5VF 10 14 C5 12 11 U1 9 0.1F 4 2 74HCT74 8 DGND 7 13 3 U1 74HCT74 DGND +5VF 1 2 1 X1 14 C6 2.2F 7 3MHZ C10 1 33pF 8 START CONVERT J1 1 B1 R6 321 50 74HCT573 DGND DGND 26 24 22 20 18 16 14 12 10 8 6 4 2 C11 2.2F 74HC86 1 3 U5 EOC 2 25 23 21 19 17 15 13 11 9 7 5 3 1 P2 SG1 AGND SG2 SG3 SG4 AGND DGND AGND ADS-933 EVALUATION BOARD ADS-933 Figure 5. ADS-933 Evaluation Board Schematic. 74HCT573 7 C7 2.2F N.C. READ FIF/DIR FST1 FST2 +5VD DGND -5VA DGND -15V +15V DGND +5VA (R) (R) ADS-933 MECHANICAL DIMENSIONS INCHES (mm) 2.12/2.07 (53.85/52.58) 40 21 Dimension Tolerances (unless otherwise indicated): 2 place decimal (.XX) 0.010 (0.254) 3 place decimal (.XXX) 0.005 (0.127) Lead Material: Kovar alloy 1.11/1.08 (28.20/27.43) Lead Finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating 1 20 0.100 TYP. (2.540) 1.900 0.008 (48.260) 0.245 MAX. (6.223) PIN 1 INDEX ( ON TOP) 0.200/0.175 (5.080/4.445) 0.015/0.009 (0.381/0.229) 0.210 MAX. (5.334) 0.018 0.002 (0.457) 0.045/0.035 (1.143/0.889) 0.110/0.090 (2.794/2.286) SEATING PLANE 0.035/0.015 (0.889/0.381) 0.900 0.010 (22.86) 0.110/0.090 (2.794/2.286 ORDERING INFORMATION OPERATING TEMP. RANGE 0 to +70C -55 to +125C ANALOG INPUT Bipolar (2.75V) Bipolar (2.75V) MODEL ADS-933MC ADS-933MM ACCESSORIES ADS-B933 HS-40 Evaluation Board (without ADS-933) Heat Sink for all ADS-933 models Receptacles for PC board mounting can be ordered through AMP, Inc., Part # 3-331272-8 (Component Lead Socket), 40 required. For MIL-STD-883 product, or surface mount packaging, contact DATEL. (R) (R) ISO 9001 R E G I S T E R E D INNOVATION and EXCELLENCE DS-0367P 05/97 DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356 Internet: www.datel.com E-mail: sales@datel.com Data sheet fax back: (508) 261-2857 DATEL (UK) LTD. Tadley, England Tel: (01256)-880444 DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 01-34-60-01-01 DATEL GmbH Munchen, Germany Tel: 89-544334-0 DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025 DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark. |
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